1. Field of the Invention
The present invention relates to three dimensional integrated circuit (3D IC) devices.
Some monolithic 3D approaches and other inventive concepts relevant to this document are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,298,875, 8,642,416, 8,163,581, 8,378,715, 8,379,458, 8,450,804, 8,574,929, 8,581,349, 8,687,399, 8,742,476, 8,674,470, 8,902,663, 8,803,206; US patent publication 2013/0020707; and pending U.S. patent application Ser. Nos. 13/862,537, 13/836,080, 62/077,280, 62/042,229, Ser. Nos. 13/803,437, 14/298,917, 61/932,617, and Ser. No. 14/607,077. The contents of the foregoing patents, publications, and applications are incorporated herein by reference.
2. Background
Three dimensional integrated circuits are known in the art, though the field is in its infancy with a dearth of commercial products. Many manufacturers sell multiple standard two dimensional integrated circuit (2DIC) devices in a single package known as a Multi-Chip Modules (MCM) or Multi-Chip packages (MCP). Often these 2DICs are laid out horizontally in a single layer, like the Core 2 Quad microprocessor MCMs available from Intel Corporation of Santa Clara, Calif. In other products, the standard 2DICs are stacked vertically in the same MCP like in many of the moviNAND flash memory devices available from Samsung Electronics of Seoul, South Korea like the illustration shown in FIG. 9C. None of these products are true 3DICs.
Devices where multiple layers of silicon or some other semiconductor (where each layer comprises active devices and local interconnect like a standard 2DIC) are bonded together with Through Silicon Via (TSV) technology to form a true 3D IC have been reported in the literature in the form of abstract analysis of such structures as well as devices constructed doing basic research and development in this area. FIG. 9A illustrates an example in which Through Silicon Vias are constructed continuing vertically through all the layers creating a global interlayer connection. FIG. 9B provides an illustration of a 3D IC system in which a Through Silicon Via 404 is placed at the same relative location on the top and bottom of all the 3D IC layers creating a standard vertical interface between the layers.
Constructing future 3DICs will require new architectures and new ways of thinking. In particular, yield and reliability of extremely complex three dimensional systems will have to be addressed, particularly given the yield and reliability difficulties encountered in complex Application Specific Integrated Circuits (ASIC) built in recent deep submicron process generations. In this specification the terms stratum, tier or layer might be used for the same structure and they may refer to transistors or other device structures (such as capacitors, resistors, inductors) that may lie substantially in a plane format and in most cases such stratum, tier or layer may include the interconnection layers used to interconnect the transistors on each. In a 3D device as herein described there may at least two such planes called tier, or stratum or layer.
Fortunately, current testing techniques will likely prove applicable to 3D IC manufacturing, though they will be applied in very different ways. FIG. 28 illustrates a prior art set scan architecture in a 2D IC ASIC 2800. The ASIC functionality is present in logic clouds 2820, 2822, 2824 and 2826 which are interspersed with sequential cells like, for example, pluralities of flip flops indicated at 2812, 2814 and 2816. The ASIC 2800 also has input pads 2830 and output pads 2840. The flip flops are typically provide with circuitry to allow them to function as a shift register in a test mode. In FIG. 28 the flip flops form a scan register chain where pluralities of flip flops 2812, 2814 and 2816 are coupled together in series with Scan Test Controller 2810. One scan chain is shown in FIG. 28, but in a practical design comprising millions of flip flops many sub-chains will be used.
In the test architecture of FIG. 28, test vectors are shifted into the scan chain in a test mode. Then the part is placed into operating mode for one or more clock cycles, after which the contents of the flip flops are shifted out and compared with the expected results. This provides an excellent way to isolate errors and diagnose problems, though the number of test vectors in a practical design can be very large and an external tester is often required.
FIG. 29 shows a prior art boundary scan architecture in exemplary ASIC 2900. The part functionality is shown in logic function block 2910. The part also has a variety of input/output cells 2920, each comprising a bond pad 2922, an input buffer 2924, and a tri-state output buffer 2926. Boundary Scan Register Chains 2932 and 2934 are shown coupled in series with Scan Test Control block 2930. This architecture operates in a similar manner as the set scan architecture of FIG. 28. Test vectors are shifted in, the part is clocked, and the results are then shifted out to compare with expected results. Typically, set scan and boundary scan are used together in the same ASIC to provide complete test coverage.
FIG. 30 shows a prior art Built-In Self Test (BIST) architecture for testing a logic block 3000 which comprises a core block function 3010 (what is being tested), inputs 3012, outputs 3014, a BIST Controller 3020, an input Linear Feedback Shift Register (LFSR) 3022, and an output Cyclical Redundancy Check (CRC) circuit 3024. Under control of BIST Controller 3020, LFSR 3022 and CRC 3024 are seeded (set to a known starting value), the logic block 3000 is clocked a predetermined number of times with LFSR 3022 presenting pseudo-random test vectors to the inputs of Block Function 3010 and CRC 3024 monitoring the outputs of Block Function 3010. After the predetermined number of clocks, the contents of CRC 3024 are compared to the expected value (or “signature”). If the signature matches, logic block 3000 passes the test and is deemed good. This sort of testing is good for fast “go” or “no go” testing as it is self-contained to the block being tested and does not require storing a large number of test vectors or use of an external tester. BIST, set scan, and boundary scan techniques are often combined in complementary ways on the same ASIC. A detailed discussion of the theory of LSFRs and CRCs can be found in Digital Systems Testing and Testable Design, by Abramovici, Breuer and Friedman, Computer Science Press, 1990, pp 432-447.
Another prior art technique that is applicable to the yield and reliability of 3DICs is Triple Modular Redundancy. This is a technique where the circuitry is instantiated in a design in triplicate and the results are compared. Because two or three of the circuit outputs are always assumed in agreement (as is the case assuming single error and binary signals) voting circuitry (or majority-of-three or MAJ3) takes that as the result. While primarily a technique used for noise suppression in high reliability or radiation tolerant systems in military, aerospace and space applications, it also can be used as a way of masking errors in faulty circuits since if any two of three replicated circuits are functional the system will behave as if it is fully functional. A discussion of the radiation tolerant aspects of Triple Modular Redundancy systems, Single Event Effects (SEE), Single Event Upsets (SEU) and Single Event Transients (SET) can be found in U.S. Patent Application Publication 2009/0204933 to Rezgui (“Rezgui”).